1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of fabricating the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, much effort is being expended to study and develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FED), and electro-luminescence displays (ELDs), as a substitute for CRTs. In particular, these types of flat panel displays have been driven in an active matrix type display in which a plurality of pixels arranged in a matrix form are driven using a plurality of thin film transistors therein. Among the active matrix types of flat panel displays, liquid crystal display (LCD) devices and electroluminescent display (ELD) devices are widely used as monitors for notebook computers and desktop computers because of their high resolution, ability to display colors and superiority in displaying moving images.
In general, an LCD device includes array and color filter substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field in the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
Recently, an active matrix type LCD device is used, where thin film transistors are arranged in a matrix manner on an array substrate. Amorphous silicon or polycrystalline silicon is used as a semiconductor layer of the thin film transistor. When hydrogenated amorphous silicon (a-Si:H) is used, low temperature process is possible, and thus a low-priced substrate can be used. However, since hydrogenated amorphous silicon has a poor electric property such as low mobility of 0.1 to 1.0 cm2/Vs, it is difficult to use hydrogenated amorphous silicon to form driving circuits directly on an array substrate. Polycrystalline silicon has mobility higher than that of hydrogenated amorphous silicon. Accordingly, when using polycrystalline silicon, driving circuits are easily formed directly on an array substrate, and a liquid crystal panel has a compact size.
FIG. 1 is a schematic plan view of an array substrate for an LCD device according to the related art.
As shown in FIG. 1, a display region D1 and a non-display region D2 are defined in a substrate 10. In the display region D1, a plurality of gate lines 12 and a plurality of data lines 14 are disposed on the substrate 10 and cross each other to define a plurality of pixel regions P. In each pixel region P, a pixel thin film transistor T and a pixel electrode 17 are disposed. The pixel thin film transistor T is an n-type or p-type.
In the non-display region D2, gate and data driving circuits 16 and 18 are disposed on the substrate 10. The gate driving circuit 16 is disposed at one side of the substrate 10 and supplies gate signals to the gate lines 12, and the data driving circuit 18 is disposed at other side of the substrate 10 and supplies data signals to the data lines 14. The gate and data driving circuits 16 and 18 include CMOS (complementary metal-oxide semiconductor) device having an n-type driving thin film transistor and a p-type driving thin film transistor.
FIG. 2 is a plan view of a display region of an array substrate for an LCD device of FIG. 1.
As shown in FIG. 2, on a substrate 30, a gate line GL is extended along a first direction, and a data line DL is extended along a second direction. The gate line GL and the data line DL cross each other to define a pixel region P. A storage line SL is extended along the first direction and spaced apart from the gate line GL.
A pixel thin film transistor T is disposed at a crossing portion of the gate and data lines GL and DL. The pixel thin film transistor T includes a gate electrode 52, a polycrystalline semiconductor pattern 38, a source electrode 74a and a drain electrode 74b. A pixel electrode 82 is disposed in the pixel region P and contacts the drain electrode 74b. A storage capacitor Cst including first, second and third storage electrodes 40, 54 and 76 is disposed in the pixel region P.
FIG. 3A is a cross-sectional view of a portion of a driving circuit for an LCD device of FIG. 1, and FIG. 3B is a cross-sectional view taken along a line III-III of FIG. 2.
As shown in FIGS. 3A and 3B, a driving circuit (a gate or data driving circuit) DC in a non-display region D2 includes a CMOS device, and the CMOS device includes a p-type driving thin film transistor T(p) and an n-type driving thin film transistor T(n).
In a pixel region P of a display region D1, a pixel electrode 82 contacting a pixel thin film transistor Ts and a pixel storage capacitor Cst are disposed. The pixel thin film transistor Ts is n-type or p-type, and an n-type thin film transistor is mainly used as the pixel thin film transistor Ts. The pixel storage capacitor Cst includes first, second and third storage electrodes 40, 54 and 76. The pixel storage capacitor Cst includes a first storage capacitor C1 and a second storage capacitor C2.
FIGS. 4A to 4I are cross-sectional views illustrating fabrication processes in a non-display region of the related art array substrate, FIGS. 5A to 5I are plan views illustrating fabrication processes in a display region of the related art array substrate, and FIGS. 6A to 6I are cross-sectional views taken along lines III-III of FIGS. 5A to 5I, respectively.
As shown in FIGS. 4A, 5A and 6A, a buffer layer 32 is formed on a substrate 30 having a display region D1 and a non-display region D2. The display region D1 has a pixel region P, a switching region A3 and a storage region A4, and the non-display region D2 has a p-type region A1 and an n-type region A2. Hydrogenated amorphous silicon (a-Si:H) is deposited on the buffer layer 32 and crystallized. The crystallized silicon (polycrystalline silicon) layer is patterned in a first mask process to form first, second, third and fourth polycrystalline semiconductor patterns 34, 36, 38 and 40 in the p-type region A1, the n-type region A2, the switching region A3 and the storage region A4, respectively. The third and fourth polycrystalline semiconductor patterns 38 and 40 are formed in one body.
As shown in FIGS. 4B, 5B and 6B, a photoresist is deposited on the substrate 30 having the polycrystalline semiconductor patterns 34, 36, 38 and 40 and patterned in a second mask process to form a photoresist pattern 42. The photoresist pattern 42 covers the p-type region A1, the n-type region A2 and the switching region A3. An ion doping process using n+ ions is performed for the fourth polycrystalline semiconductor pattern 40. By the doping process, a resistance of the fourth polycrystalline semiconductor pattern 40 is reduced. After the doping process, the photoresist pattern 42 is removed. The doped fourth polycrystalline semiconductor pattern 40 is a first storage electrode 40.
As shown in FIGS. 4C, 5C and 6C, a gate insulating layer 46 is formed on the substrate 30 having the first storage electrode 40. A metallic material is deposited on the gate insulating layer 46 and patterned in a third mask process to form first to third gate electrodes 48, 50 and 52 and a second storage electrode 54. The first to third gate electrodes 48, 50 and 52 correspond to center portions of the first to third polycrystalline semiconductor patterns 34, 36 and 38, respectively, and the second storage electrode 54 corresponds to the first storage electrode 40. In the third mask process, a gate line GL and a storage line SL are also formed.
As shown in FIGS. 4D, 5D and 6D, a photoresist is deposited on the substrate 30 having the gate electrodes 48, 50 and 52 and patterned in a fourth mask process to form a photoresist pattern 56. The photoresist pattern 56 covers the p-type region A1. An ion doping process using n+ ions is performed for the n-type region A2 and the switching region A3. Side portions of the second and third polycrystalline semiconductor patterns 36 and 38 are doped with n+ ions. The ion-doped side portions of the second and third polycrystalline semiconductor patterns 36 and 38 have an ohmic contact property. The photoresist pattern 56 is then removed.
As shown in FIGS. 4E, 5E and 6E, a photoresist is deposited on the substrate 30, where the n+ doping process is completed, and patterned in a fifth mask process to form a photoresist pattern 58. The photoresist pattern 58 covers the n-type region A2, the switching region A3 and the storage region A4. An ion doping process using p+ ions is performed for the p-type region A1. Side portions of the first polycrystalline semiconductor patterns 34 are doped with p+ ions. The ion-doped side portions of the first polycrystalline semiconductor pattern 34 have an ohmic contact property. The photoresist pattern 58 is then removed.
As shown in FIGS. 4F, 5F and 6F, an interlayer insulating film 60 is formed on the substrate 30 where the p+ doping process is completed. The gate insulating layer 46 and interlayer insulating film 60 are patterned in a sixth mask process to form first and second contact holes 62a and 62b exposing the ion-doped portions of the first polycrystalline semiconductor pattern 34, third and fourth contact holes 64a and 64b exposing the ion-doped portions of the second polycrystalline semiconductor pattern 36, and fifth and sixth contact holes 66a and 66b exposing the ion-doped portions of the third polycrystalline semiconductor pattern 38.
As shown in FIGS. 4G, 5G and 6G, a metallic material is deposited on the passivation layer 60 and patterned in a seventh mask process to form first source and drain electrodes 70a and 70b contacting the ion-doped portions of the first polycrystalline semiconductor pattern 34, second source and drain electrodes 72a and 72b contacting the ion-doped portions of the second polycrystalline semiconductor pattern 36, and third source and drain electrodes 74a and 74b contacting the ion-doped portions of the third polycrystalline semiconductor pattern 38. At the same time, a data line DL is formed, and a third storage electrode 76 extended from the third drain electrode 74b is formed in the storage region A4.
Through the above first to seventh mask processes, a CMOS device having an n-type driving thin film transistor and a p-type driving thin film transistor is formed in the non-display region D2. An n-type pixel thin film transistor is formed in the switching region A3 of the display region D1, and a pixel storage capacitor including a first storage capacitor C1 formed by the first and second electrodes 40 and 54 and a second storage capacitor C2 formed by the second and third electrodes 54 and 76 is formed.
As shown in FIGS. 4H, 5H and 6H, a passivation layer 78 is formed on the substrates 30 having the data line DL. The passivation layer 78 is patterned in an eighth mask process to form a drain contact hole 80 exposing the third storage electrode 76 (or the third drain electrode 74b).
As shown in FIGS. 4I, 5I and 6I, a transparent conductive material is deposited on the passivation layer 78 and patterned in a ninth mask process to form a pixel electrode 82. The pixel electrode 82 is connected to the third drain electrode 74b through the drain contact hole (80 of FIG. 6H).
Through the above first to ninth mask processes, the related art array substrate having the driving circuit directly formed thereon is fabricated. As the mask processes increases, product cost also increases and productivity decreases. Therefore, reduction of the mask processes is needed.